FIELD OF THE INVENTION
The present invention generally relates to semiconductor memory circuits, and more particularly to a semiconductor memory circuit having a test mode enabled in response to a command.
Recently, the speedup of CPUs has required semiconductor devices such as DRAMs (Dynamic Random Access Memories) to input and output data at a higher signal frequency and increase the data transfer rate. As semiconductor memory circuits capable of satisfying such a requirement, there are known a synchronous dynamic random access memory (SDRAM) and a fast cycle random access memory (FCRAM), which memories operate in synchronism with a clock signal supplied from the outside of the circuits.
Generally, semiconductor devices which operate at a high speed are equipped with a test mode directed to determining whether the semiconductor devices operate normally. The semiconductor devices can shift to the test mode from a normal mode by a given combination of signals supplied from the outside. Hereinafter, the shift from the normal mode to the test mode will be referred to as a test mode entry.
A description will now be given of the test mode entry in a synchronous DRAM (SDRAM).
FIG. 1 is a block diagram of an SDRAM 1, which includes a block buffer 10, a command decoder 11, an address buffer/register&bank select circuit 12, an I/O data buffer/register 13, control signal latch circuits 14, a mode register 15, column address counters 16, a test mode enable control circuit 17, a test mode decoder 18, a bank-0 circuit 19 and a bank-1 circuit 20.
Each of the bank-0 circuit 19 and the bank-0 circuit 20 includes a plurality of memory cell blocks 25a, 25b, 25c and 25d, and a write amplifier/sense buffer 26. Each of the memory cell blocks 25a-25d includes memory cells 21 arranged in a matrix formation, a row decoder 22, and a sense amplifier block 23.
The cell matrix (which is also referred to as a core circuit) having the memory cells arranged in the matrix formation is divided into parts on the bank basis. Each of the bank-based divided cell matrixes is divided into blocks 25a-25d. In each of the blocks 25a-25d, the memory cells are arranged in rows and columns. Each of the blocks 25a-25d is equipped with the sense amplifier block 23. Although the SDRAM 1 shown in FIG. 1 has two banks, an arbitrary number of banks can be defined in the SDRAM 1.
A description will be given of the functions of the structural parts which form the SDRAM 1. The clock buffer 10 receives a clock signal CLK and a clock enable signal CKE from the outside, and supplies an internal synchronous clock signal CLK1 based on the clock enable signal CKE to the structural parts. The clock enable signal CKE is supplied to the command decoder 11, the address buffer/register&bank select circuit 12, and the I/O data buffer/register 13.
The command decoder 11 is externally supplied with a chip select signal/CS, a row address strobe signal/RAS, a column address strobe signal/CAS, and a write enable signal/WE. The command is defined by the combination of the above-mentioned control signals. A decoded command is then supplied to the control signal latch circuit 14, the mode register 15 and the test mode enable control circuit 17. The control signal latch circuit 14 latches the decoded command supplied from the command decoder 11, and supplies it to the bank-0 circuit 19 and the bank-1 circuit 20. The symbol "/" denotes the active-low logic.
The address buffer/register&bank select circuit 12 is supplied with a memory address signal consisting of address bits A0-An from the outside. Then, the memory address signal of bits A0-An is supplied to the mode register 15, the column address counter 16, and the test mode enable control circuit 17. The most significant bit An of the memory address signal is used as a bank select signal and selects either the bank-0 circuit 19 or the bank-1 circuit 20.
The I/O data buffer/register 13 receives data signals DQ0-DQn and a data input/output mask signal DQM from the outside. The data signals DQO-DQn received from the outside are supplied to the bank-0 circuit 19 and the bank-1 circuit 20. Also, the I/O data buffer/register 13 receives data signals DQO-DQn from the bank-0 circuit 19 and the bank-1 circuit 20. The data input/output mask signal DQM masks the input/output data signals DQO-DQn as necessary.
The mode register 15 is equipped with a register which stores data indicating the burst length in the data read/write operation. The data indicating the burst length is described by the decoded command and the memory address signal and is set in the mode register 15. The above data is supplied to the column address counters 16 as burst length information. The column address counters 16 generate column address signals from the memory address signal supplied from the address buffer/register&bank select circuit 12, and output the column address signals to the bank-0 circuit 19 and the bank-1 circuit 20.
The test mode enable control circuit 17 determines whether the test mode entry should be permitted on the basis of the combination of a mode register set command MRS and the memory address signal. The mode register set command MRS is a command defined by the row address strobe signal/RAS, the column address strobe signal/CAS and the write enable signal/WE. When the test mode entry is permitted, the test mode enable control signal 17 supplies a test mode entry to the test mode decoder 18.
The test mode decoder 18 generates test mode signals indicative of respective test modes on the basis of the combination of the test mode entry signal and the memory address signal. The test mode signals are then supplied to the structural parts related to the respective test modes.
A description will now be given of the structure of the bank-0 circuit 19 and the functions thereof. The structure of the bank-1 circuit 20 and the functions thereof are the same as those of the bank-0 circuit 19.
In the bank-0 circuit 19, data stored in the memory cells 21 of the blocks 25a, 25b, 25c and 25d are supplied to the sense amplifier block 23. For example, in the block 25a, the row decoder 22 generates a word line select signal for selecting the word line specified by the memory address signal A0-An. The sense amplifier block 23 receives and holds data stored in the memory cells 21 connected to the selected word line. The column decoder 24 generates column line select signals for simultaneously selecting a plurality of bits of the data stored in the sense amplifier block 23, which has sense amplifiers provided to the respective bit lines.
At the time of reading data, the write amplifier/sense buffer 26 receives parallel data read from the selected block and outputs the parallel data to a write data bus. At the time of writing data, the write amplifier/sense buffer 26 buffers the received parallel data and outputs the buffered parallel data to a global data bus, which is coupled to the bit line via a column gate provided in the block of the column decoder 24 and controlled thereby.
A description will be given of a structure of the test mode enable control circuit 17 and the functions thereof by referring to FIG. 2. As shown in FIG. 2, the circuit 17 is made up of NAND circuits 100, 110, 120, 130 and 150, and NOT circuits 140 and 160.
The NAND circuit 100 receives the memory address signal A7 from the address buffer/register&bank select circuit 12 and the mode register set command MRS from the command decoder 11, and outputs a resultant signal to the NAND circuit 130. The NAND circuit 110 receives the memory address signal A8 from the address buffer/register&bank select circuit 12 and a reset command signal from the command decoder 11, and outputs a resultant signal to the NAND circuit 120.
The NAND circuit 120 receives the output signal of the NAND circuit 110 and a power-on signal, and outputs a resultant signal to the NAND circuit 150 via the NOT circuit 140. The NAND circuit 130 receives the output signals of the NAND circuits 100 and 150, and outputs a resultant signal to the NAND circuit 150. The NAND circuit 150 receives the signal from the NOT circuit 140 and the output signal of the NAND circuit 130, and supplies the test mode entry signal to the test mode decoder 18 via the NOT circuit 160.
The NAND circuits 130 and 150 and the NOT circuits 140 and 160 form a latch circuit 17, which supplies the test mode entry signal to the test decoder 18 at the time of the test mode. Also, the latch circuit 170 stops outputting the test mode entry signal on the basis of the memory address signal A8, the reset command signal and the power-on signal.
As described above, the test mode enable control circuit 170 controls the outputting of the test mode entry signal on the basis of the memory address signals A7 and A8 from the address buffer/register&bank select circuit 12, the mode register set command MRS and the reset command signal from the command decoder 11, and the power-on signal.
However, there is a possibility that the test mode entry signal may accidentally be generated because the test mode entry signal is based on the mode register set command MRS which is defined by the combination of the chip select signal/CS, the row address strobe signal/RAS, the column address strobe signal/CAS and the write enable signal/WE. The above possibility is high particularly at the time of power on because the signals are not yet settled.